MOSFET characteristic examples (Reference)

(Shindengen Electric Manufacturing Co., Ltd. products)

Type No.	VDSS	ID	RDS(ON)
P60B6SN	60V	60A	5.3mΩ
P4B60HP2	600V	4A	1.5Ω

This is a comparison of the RDS(ON) of a low VDSS MOSFET and
high VDSS MOSFET using the same package.
The size of the bare dies is nearly the same, but there is this much of a difference in RDS(ON).

Diode characteristic examples (Reference)

(Shindengen Electric Manufacturing Co., Ltd. products)

Type No.	VRRM	IF	VF
D1FS6A (SBD)	60V	2.6A	0.57V
D1F60A (General Di)	600V	1.2A	0.97V

Diode VF does not rely on VRRM as much as MOSFET RDS(ON).

What is ON resistance?

RDS(ON) details

Differences in drift layer between high and low VDSS MOSFETs

If voltage is applied between D-S, a depletion layer will extend to the N-layer based on the voltage.
The MOSFET VDSS is determined by the size (thickness) of the depletion layer on the N-layer.

From this you can see that there is a “minimum resistance value” based on the required VDSS.

In order to lower RDS(ON)

1. Manufacture a single bare die with a large number of clustered  cells
   ⇒This is the basic methodology, however concentrating a large number of clustered cells will increase the bare die size and also increase the cost.
2. Make each cell as small as possible
   ⇒If channel length is shortened, the channel resistance per each individual cell will decrease, allowing for a higher concentration of cells on the same bare die area.
3. Utilize cell layout orientation
   ⇒This is what the trench technique consists of.  Requires specialized processing for etching trenches.
4. Lower the resistance of components other than the channel
   ⇒A variety of techniques are utilized to lower resistance including lowering the resistance of the drift layer which increases VDSS, using connectors instead of wires, increasing lead frame and terminal thickness, etc.
   
   

Major technologies for lowering RDS(ON)

	Degree of effectiveness		Details and aims
	Low withstand voltage MOSFETs	High withstand voltage MOSFETs
Process miniaturization	◎	〇	The fundamental semiconductor processing technique. Equipment capacity. Reduces channel resistance and miniaturizes cells.
Trench gates	◎	△	Technology where trenches are etches and gates are embedded. The main technique for low VDSS MOSFETs. Increases cell density.
Clips (connectors)	◎	△	Metallic conductors are used for connections instead of wires. Lowers not only resistance, but also inductance.
Super Junction	✕	◎	PN stripe structures are created on the drift layer. Lowers RDS(ON) below previous theoretical limitations.
Wide Band Gap	△	◎	Introduction of new materials such as SiC and GaN. Allows for characteristics which were not achievable with Si.

Super Junction and Wide Band Gap are technologies for lowering drift layer resistance which are used in high VDSS MOSFETs.

Effects of RDS(ON) and capacitive components on circuit characteristics